1. Field of the Invention
The present invention is related to a delay lock loop, a loop filter, and a method of phase locking of a delay lock loop, and particularly to a delay lock loop that has a switched capacitor loop filter, a loop filter that has a switched capacitor, and a method of phase locking of a delay lock loop that has a switched capacitor loop filter.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a delay lock loop 100 according to the prior art. The delay lock loop 100 includes a phase frequency detector 102, a charge pump 104, a voltage control delay line 106, and a capacitor C. The phase frequency detector 102 is used for receiving a reference clock REF and a feedback clock FB, and outputting an upper switch signal UP or a lower switch signal DN according to the reference clock REF and the feedback clock FB. The charge pump 104 is used for charging or discharging according to the upper switch signal UP or the lower switch signal DN, and outputting a control voltage VCTRL (that is, a voltage of the capacitor C). The voltage control delay line 106 adjusts the feedback clock FB to synchronize the reference clock REF and the feedback clock FB according to the control voltage VCTRL and the reference clock REF. In addition, an enabling signal CKE can enable and disable the delay lock loop 100.
Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a diagram illustrating decrease of the control voltage VCTRL due to leakage of the capacitor C when the delay lock loop 100 enters a power down mode, and FIG. 2B is a diagram illustrating the delay lock loop 100 having a phase error due to the decrease of the control voltage VCTRL when the delay lock loop 100 is enabled again. When the delay lock loop 100 enters the power down mode (that is, the enabling signal CKE for enabling the delay lock loop 100 is at a logic-low voltage), the phase frequency detector 102, the charge pump 104, and the voltage control delay line 106 are disabled. Therefore, amount of charge stored in the capacitor C is decreased gradually until the delay lock loop 100 is enabled again. As shown in FIG. 2A, when the delay lock loop 100 is in the power down mode, voltage variation caused by decreasing charge of the capacitor C with a large capacitance (large resistor-capacitor time constant) is less than voltage variation caused by decreasing charge of the capacitor C with a small capacitance (small resistor-capacitor time constant). Therefore, as shown in FIG. 2B, when the delay lock loop 100 leaves the power down mode (that is, the enabling signal CKE for enabling the delay lock loop 100 is at a logic-high voltage), a phase error caused by the capacitor C with the large capacitance is less than a phase error caused by the capacitor C with the small capacitance.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the charge pump 104. When the charge pump 104 receives the upper switch signal UP, an upper current source 1042 charges the capacitor C according to a current IU; when the charge pump 104 receives the lower switch signal DN, the lower current source 1044 discharges the capacitor C according to a current ID, where the current IU is equal to the current ID. Loop bandwidth Wn of the delay lock loop 100 is determined by equation (1):
                    Wn        =                              IU            ×                          K              VCDL                                            T            ×            C                                              (        1        )            
As shown in equation (1), KVCDL is a gain of the voltage control delay line 106, and T is a period of the reference clock REF of the delay lock loop 100. In addition, a locking time LT of the delay lock loop 100 and the loop bandwidth Wn are inversely proportional. Therefore, the delay lock loop 100 with the capacitor C with the small capacitance has shorter locking time LT. However, the feedback clock FB outputted by the delay lock loop 100 with the capacitor C with the small capacitance has large jitter.
In the prior art, the delay lock loop 100 usually has a capacitor C with a large capacitance to reduce jitter of the feedback clock FB and the leakage of the capacitor C when the delay lock loop 100 enters the power down mode, and the delay lock loop 100 also has large charging/discharging currents (IUID) to reduce the locking time LT. However, the delay lock loop 100 with the capacitor C with the large capacitance has a problem of large power consumption due to the large charging/discharging currents.